This invention relates to a MOS integrated circuit including an isolation gate type FET.
In a MOS integrated circuit of, for example, a symmetrical complementary metal oxide semiconductor (C-MOS) type, other circuit patterns are often formed, from the IC pattern design consideration, between the source electrode of a MOS transistor and the source electrode circuit i.e. a source power supply circuit (+VDD or -VSS). Such circuit patterns are used primarily for connection between elements in an IC chip or between these elements and external terminals. The reason why such circuit patterns are formed between the source electrode and the source power supply circuit is as follows. The circuit pattern made of an electroconductive material is formed on a semiconductor pattern with an insulation or possivation film such as SiO.sub.2 therebetween. Thus, a capacitor is formed between the circuit pattern and the semiconductor pattern. If such a capacitor is formed on the drain pattern side of the MOS transistor an output capacitance is increased, lowering the switching speed. The source pattern side of the MOS transistor is connected to the source power supply circuit where a potential is at a substantially zero level, and shows a lower circuit impedance. If, therefore, an additional capacitance is formed by the circuit pattern there is no possibility that the switching speed of the MOS transistor will be lowered due to the presence of the additional capacitance.
For the above-mentioned reason, there is more chance that the circuit pattern will be formed between the source electrode of MOS transistors and the source power supply circuit unless there is no particular design requirement. Where in this way many circuit patterns are formed at the source side of the MOS transistors, a greater spacing is necessarily required between the source electrode and the source power supply circuit. An electrical connection between the source electrode and the source power supply circuit is provided by a high impurity concentration N.sup.+ or P.sup.+ layer from the standpoint of an IC manufacturing process. For example, the source electrode of the p-channel MOS transistor is provided by a P.sup.+ layer formed in an N-type substrate and a connection between the source electrode and the source power supply circuit is effected through the P.sup.+ layer. The P.sup.+ layer, unlike a metal, has a relatively high resistivity. For this reason, if a spacing between the source electrode and the source power supply circuit is made greater, a source diffusion resistance R.sub.S of appreciable value will be formed in the source circuit of the MOS transistor. The source diffusion resistance R.sub.S provides a current negative-feedback effect on a source-grounded MOS transistor. This current negative-feedback increases an output impedance of the MOS transistor and decreases an effective or equivalent transconductance gm. The diffusion resistance R.sub.S also increases an output resistance Ro when the MOS transistor is completely in the conductive state (such resistance is hereinafter referred to as a turn-ON resistance). An increase in the turn-ON resistance lowers the maximum output current of the MOS transistor. The decrease of the transconductance gm and increase of the output impedance increases the time constant of an integrator circuit comprising an output capacitance and an output impedance and, as a result, the switching speed is lowered. When a greater diffusion resistance is formed in the source circuit of the MOS transistor the maximum output current or fan-out is decreased with the result that the switching speed is lowered.
The same thing can also be said about an N-channel MOS transistor formed in a P.sup.+ type substrate.